NXP Semiconductors /MIMXRT1062 /USDHC1 /HOST_CTRL_CAP

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Interpret as HOST_CTRL_CAP

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SDR50_SUPPORT)SDR50_SUPPORT 0 (SDR104_SUPPORT)SDR104_SUPPORT 0 (DDR50_SUPPORT)DDR50_SUPPORT 0TIME_COUNT_RETUNING 0 (USE_TUNING_SDR50_0)USE_TUNING_SDR50 0 (RETUNING_MODE_0)RETUNING_MODE 0 (MBL_0)MBL0 (ADMAS_0)ADMAS 0 (HSS_0)HSS 0 (DMAS_0)DMAS 0 (SRS_0)SRS 0 (VS33_0)VS33 0 (VS30_0)VS30 0 (VS18_0)VS18

RETUNING_MODE=RETUNING_MODE_0, ADMAS=ADMAS_0, VS18=VS18_0, VS30=VS30_0, HSS=HSS_0, VS33=VS33_0, DMAS=DMAS_0, MBL=MBL_0, USE_TUNING_SDR50=USE_TUNING_SDR50_0, SRS=SRS_0

Description

Host Controller Capabilities

Fields

SDR50_SUPPORT

SDR50 support

SDR104_SUPPORT

SDR104 support

DDR50_SUPPORT

DDR50 support

TIME_COUNT_RETUNING

Time Counter for Retuning

USE_TUNING_SDR50

Use Tuning for SDR50

0 (USE_TUNING_SDR50_0): SDR does not require tuning

1 (USE_TUNING_SDR50_1): SDR50 requires tuning

RETUNING_MODE

Retuning Mode

0 (RETUNING_MODE_0): Mode 1

1 (RETUNING_MODE_1): Mode 2

2 (RETUNING_MODE_2): Mode 3

MBL

Max Block Length

0 (MBL_0): 512 bytes

1 (MBL_1): 1024 bytes

2 (MBL_2): 2048 bytes

3 (MBL_3): 4096 bytes

ADMAS

ADMA Support

0 (ADMAS_0): Advanced DMA Not supported

1 (ADMAS_1): Advanced DMA Supported

HSS

High Speed Support

0 (HSS_0): High Speed Not Supported

1 (HSS_1): High Speed Supported

DMAS

DMA Support

0 (DMAS_0): DMA not supported

1 (DMAS_1): DMA Supported

SRS

Suspend / Resume Support

0 (SRS_0): Not supported

1 (SRS_1): Supported

VS33

Voltage Support 3.3V

0 (VS33_0): 3.3V not supported

1 (VS33_1): 3.3V supported

VS30

Voltage Support 3.0 V

0 (VS30_0): 3.0V not supported

1 (VS30_1): 3.0V supported

VS18

Voltage Support 1.8 V

0 (VS18_0): 1.8V not supported

1 (VS18_1): 1.8V supported

Links

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